1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory containing an erase gate, and to a manufacturing method for the nonvolatile semiconductor memory containing the erase gate.
2. Description of Related Art
A memory device such as a flash memory and an electrically erasable programmable read-only memory (EEPROM) is a nonvolatile semiconductor device capable of being electrically erased and programmed. A memory cell in this type of nonvolatile semiconductor device is usually a transistor containing a floating gate and a control gate. The control gate is in some cases stacked on the floating gate, and in some cases formed at least on a channel region to a side of the floating gate. A type of the latter memory cell is called a “split-gate” and type memory cell, and is superior in terms of higher read speed and in controlling over-erasure.
A typical data programming/erasing method for the memory cell is as follows. Data programming is implemented by the Channel Hot Electron (CHE) method. More specifically, a specified program voltage potential is applied to the respective control gate and drain, and hot electrons emitted in the vicinity of the drain are injected into the floating gate. Data erasure however is implemented by the Fowler-Nordheim (FN) tunneling method. More specifically, a high voltage potential is applied to the control gate, and electrons within the floating gate are extracted via the tunnel insulation film to the control gate by FN tunneling.
Here, the following problem is encountered. The control gate in the above-described split-gate type memory cell is formed on the channel region via a gate insulation film. Moreover, to achieve FN tunneling during data erasure, a high voltage potential must be applied to the control gate as described above. The gate insulation film directly below the control gate where the high-voltage potential is applied, cannot be thinned (i.e., reduced in thickness) due to the need for reliability. Failing to thin the gate insulation film between the channel region and the control gate causes problems of a reduced read current during data read, and a drop in the read speed.
To resolve the aforementioned problems, a technology was disclosed (See JP-A No. 2001-230330, JP-A No. 2000-286348) for forming an “erase gate” for data erasure that is separate from the control gate. During data erasure, a high voltage potential is applied to this erase gate rather than the control gate. Consequently, FN tunneling then extracts electrons within the floating gate to the erase gate. The gate insulation film directly below the control gate can therefore be made thin because a high voltage potential no longer has to be applied to the control gate during data erasure. A drop in the read speed is therefore also prevented.
In the technology disclosed in JP-A No. 2001-230330, the erase gate is stacked via an insulation film on the floating gate, and the control gate is formed to a side of a laminated structure made up of the floating gate and the erase gate. In the technology disclosed in JP-A No. 2000-286348, the erase gate is formed on a source region of a semiconductor substrate surface, and formed so as to adjoin an entire side of the floating gate and a portion of an upper surface of the floating gate via a tunnel oxide film.